The present invention relates to an integrated circuit including a logic cell and, more particularly, to a state retention power gated cell.
In current integrated circuits (IC), low power consumption is an important concern, particularly for mobile devices where power storage is limited. In this regard, a number of electronic devices have a normal operation mode in which the ICs in the device are powered so that they can operate normally, for example, at high speed (frequency), and a standby (or sleep) state in which a part of (or, even most of) the ICs are powered down. However, even in the power down or sleep state, the operation state (associated information) of some of the circuits must be retained.
One way to retain state is to use a logic cell, for example, a State Retention Power Gated (SRPG) cell, to retain necessary information when in the standby or sleep mode. An SRPG cell has two power supplies. A primary power supply (VDD) is used to power the logic cell in the operational mode and a secondary power supply (VDDC) is used to power part of the circuitry that is not shut down in the standby or sleep mode. SRPG cells are well known in the art, and a typical SRPG cell may be a flip-flop, for example, such as a cascaded RS flip-flop.
As regards the cell layout, the cell can be arranged in a single row or multiple rows, that is, the circuits in the SRPG cell can be arranged into a single row or multiple rows. SRPG cells with one row arrangement are often termed as single-row-height while SRPG cells with a multiple row arrangement are termed multi-row-height SRPG cells.
In current SRPG cells, the second power supply VDDC consumes a lot of routing resources, which results in high routing congestion and low utilization in Sea of Gates (SOG). The low utilization of the SOG can cause a need for an increased die size. Further, some of the circuitry, for example, MOS transistors, of the SRPG cell is continuously powered in the standby mode, resulting in relatively high well-leakage.
It should be understood that the drawings are merely illustrative and not intended to limit the scope of the present invention. In the drawings, components have not been drawn strictly to scale or shown according to their actual shapes. Some components (e.g., layers or parts) may be enlarged relative to others, to more clearly explain the principles of the present invention. It should also be understand that the drawings are simplified illustrations of the layout plan views so as not to obscure the gist of the present invention.